The present invention relates to fabrication of high-voltage high-density CMOS integrated circuits.
A limitation to extending CMOS technology to high voltages with short channels, say 20 V and 4 microns, is imposed by gate field induced breakdown of the N-channel drains, hot-electron emission due to impact ionization, and by drain to source punchthrough.
In digital CMOS circuits parasitic substrate currents caused by impact ionization flow during the switching transients when both N and P-channel devices are turned on. This can give rise to `substrate bounce` which could cause latch-up, debiasing or the discharge of floating nodes. (These are good reasons for using epi on a P+ substrate.) In analog circuits the situation is potentially more serious since N-channel source follower type configurations could be biased such that a significant parasitic substrate current flows continuously. Perhaps the most serious effect of all is hot carrier injection into the gate oxide which can cause long term threshold shifts and transconductance degradation. Of course, all these problems become more severe as the gate oxide is scaled while the supply voltage is kept constant.
Since the coefficient of impact ionization is orders of magnitude higher for electrons than for holes, the above undesirable effects are strongest in the N-channel device, which therefore is the key to realizing short channel devices for high voltage high-density IC applications. The present invention teaches techniques for making the N-channel device in a CMOS process `hot-carrier resistant`. The inventive techniques result in formation of lightly doped N regions between the channel and the N+ a source/drain regions. This structure spreads the potential gradient at the drain pinch-off region into the N- extension. This reduces the peak electric field, thereby increasing the drain breakdown voltage, reducing impact ionization, and consequently reducing hot-electron emission.
The advantages of such a drain doping profile in reducing impact ionization have been previously published. See Ogura et al, "Design and Characteristics of the Lightly Doped Drain/Source (LDD) Insulated Gate Field Effect Transistor," Solid State Cir. 424 (1980), which is hereby incorporated by reference.
The present invention is innovative in teaching the device parameters which permit use of a lightly doped drain (LDD) doping profile in a very high voltage CMOS process. The present invention is also innovative in teaching an advantageous method for fabrication of lightly doped drain doping profiles in a CMOS technology.
Thus it is an object of the present invention to provide a method for fabrication of high-voltage high-density CMOS integrated circuits.
It is a further object of the present invention to provide a method for fabrication of CMOS integrated circuits in which the N-channel devices comprise lightly doped drain extensions.
It is a further object of the present invention to provide a method for fabrication of high-voltage high-density CMOS integrated circuits in which only the N-channel devices and not the P-channel devices comprise lightly doped drain regions, without introducing any additional masking steps.
One method which has been taught in the literature for fabrication of MOS devices with lightly doped drain regions in use of a reachthrough implant which is partially screened by a sidewall oxide. This provides a lightly doped drain region which is self-aligned to the gate edge. However, one important difficulty of sidewall oxide methods is that, unless an additional mask is added, sidewall oxide methods are inherently nonselective. That is, all devices of the type exposed (e.g. all N-channel devices, or all devices on the chip) will receive sidewall oxides, and will therefore be formed with lightly doped drain regions. This inability to selectively provide lightly doped drain regions is disadvantageous, since it cuts out several design alternatives. First, as will be discussed, lightly doped drain regions impose a substantial penalty in transconductance (source resistance) and in total series resistance. Devices which are not exposed to a high source/drain voltage would not need the LDD structure to achieve small geometries, and, if they did not have the LDD structure, could avoid the transconductance and series resistance penalties. Thus, it would be desirable for the circuit designer to have the option of providing more than one operating voltage on the chip. It can also be useful, where both analog and digital circuits are formed on the same chip, to make use of the lightly doped drain structures selective. For example, the analog circuits may need to withstand a substantially higher peak voltage than the digital circuits do.
Thus it is an object of the present invention to provide a method for forming lightly doped drain structures selectively in some but not all N-channel devices in a CMOS high-voltage process, without requiring any additional masking levels.
It should be noted that the function of lightly doped drain structure is substantially different in high voltage devices than in the VLSI approaches discussed, e.g., in the Ogura et al paper cited above. In VLSI applications, the lightly doped drain structure is of primary importance in avoiding substrate parasitic current, and also in minimizing hot carrier injection into the gate oxide. By contrast, in a high-voltage process the key question is not suppression of parasitic currents, but simply the capability to use a reasonably short channel at all. That is, the problem in high-voltage applications is to achieve (e.g.) 4 micron channel length in a functional device of any kind, whereas the problem in VLSI applications is to minimize the parasitic substrate current in (e.g.) a 11/4 micron channel length device.
Thus it is an object of the present invention to provide a CMOS technolgy having high-voltage short-channelling functional devices.
To achieve these and other objects of the invention, the present invention uses a blanket implant (preferably phosphorus) to form the lightly doped drain extension. This implant is performed after the gate level has been formed, and is preferably done with the photoresist which was used for patterning the gate level still in place. The LDD implant is counterdoped, in the PMOS devices, by the P+ source drain implant, but this LDD implant will form the lightly doped drain extension regions whereever it is not swamped by the N+ source/drain implant or counterdoped by the P+ source/drain implant. The N+ source/drain regions are then patterned. The mask used at this step leaves photoresist not only over the N-tank regions, but also over the gate levels of selected N-channel devices. These N-channel devices, and no others, wind up with lightly doped drain extension regions.
According to the present invention there is provided:
A method for fabricating CMOS integrated circuits, comprising the steps of:
providing a semiconductor substrate having a first conductivity type;
defining a plurality of moat regions on the surface of said substrate;
introducing impurities into the surface of said substrate, to form a plurality of second-type tank regions;
depositing and patterning a first insulated conductive layer to define gates in a predetermind plurality of locations;
introducing a small concentration of an N-type impurity into a shallow surface depth of all exposed regions of said substrate;
introducing a large concentration of a P-type impurity to form P-channel source/drain regions in respective predetermined locations;
forming a masking layer to cover predetermined P-channel devices, and also to cover portions of said first insulated conductive layer in respective predetermined locations of high-voltage N-channel transistors, said masking layer being locally wider than said respective portions of said insulated conductor in said respective locations of said high-voltage N-channel transistors;
introducing a large concentration of an N-type dopant into all exposed surface regions of said substrate to form N-type source/drain regions;
whereby portions of said small-concentration shallow introduction of N-type impurities form LDD regions in said predetermined high-voltage N-channel transistor locations between said respective channel regions of said high-voltage N-channel transistors and said respective source/drain regions thereof;
wherein said high-voltage N-channel transistors each comprise a channel length which is not less than 3 microns.